Precharge control signal generator, and semiconductor memory device using the same

ABSTRACT

A semiconductor memory device generates a precharge control signal asynchronous from a clock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a synchronous memory device, and inparticular to an improved synchronous memory device having anasynchronous precharge function which can input an interval betweencommands regardless of a clock period. It accomplishes this bygenerating a precharge control signal asynchronous with respect to aclock signal by using a clock enable signal or chip selector bar signalwhich is not synchronous with the clock signal.

2. Description of the Background Art

A conventional synchronous DRAM will now be explained with reference toFIGS. 1 through 5. FIG. 1 (Prior Art) is a block diagram illustrating aconventional synchronous memory device. The conventional synchronousDRAM includes a command buffer 20 receiving external commands such as aclock signal CLK, a chip selector signal /CS, a ras bar signal /RAS, acas bar signal /CAS and a write bar signal /WE; an address buffer 22receiving external addresses A0-Ai; and a data IN/OUT buffer 24receiving and outputting data signals DQ0-DQj.

The conventional synchronous DRAM also includes a command decoder 26receiving the output signals /CSI, /RASI, /CASI, /WEI from the commandbuffer 20, and generating a precharge control signal PREI forcontrolling the internal operation, a write signal W, an active signalACT, a read signal R and a mode selection signal MS. A mode register 28receives the output signal from the address buffer 22 and the modeselection signal MS from the command decoder 26, and controls anoperation mode. A test mode detector 34 receives the address signal A0and the output signal from the mode register 28, and generates a testmode detection signal TEST. A precharge control signal generator 60comprising a TPRE signal generator 36 receives the write signal W fromthe command decoder 26, the write enable signal /WEI from the commandbuffer 20, and the detection signal TEST from the test mode detector 34,and generates a test mode precharge control signal TPRE. An OR gate 38ORs the precharge control signal PREI from the command decoder 26 andthe TPRE signal from the TPRE signal generator 36, and generates aprecharge control signal PRE.

In addition, the conventional synchronous DRAM includes a column addresslatch unit 30 latching the column address signal from the address buffer22, and is generating a column address latch signal CA. A column decoder40 decodes the column address latch signal CA from the column addresslatch unit 30, and selects a bit line of a memory cell array unit 50. Arow address latch unit 32 receives the address signal from the addressbuffer 22, and generates a row address latch signal RA. A row decoder 42decodes the row address latch signal RA from the row address latch unit32, and selects a word line of the memory cell array unit 50.

The conventional synchronous DRAM includes a precharge/equalize unit 44precharging and equalizing a bit line potential of the memory cell arrayunit 50 into half a potential 1/2Vcc according to the precharge controlsignal PRE from the OR gate 38, when data are not written/read to/fromthe memory cell array 50. A sense amplifier unit 46 precharges andequalizes the bit line potential into half a potential 1/2Vcc accordingto the precharge control signal PREI, when data are not written/readto/from the memory cell array 50, and amplifies data of the bit line,when data are written/read to/from the memory cell array 50. I/O unit 48connects the data inputted/outputted through the data IN/OUT buffer 24to the sense amplifier unit 46.

FIG. 2 (Prior Art) is a block diagram of a conventional synchronousmemory array. The memory array includes a memory cell 56 comprising oneNMOS transistor N and one capacitor Cs. One terminal of the capacitor Csis connected to the NMOS transistor N through a resistor Rc, and theother terminal is supplied with cell plate voltage VPLT. If an word lineWL is selected according to an address signal and then sense amplifierenable signal SAEN is activated, a sense amplifier 53 amplifies data ofthe bit line BL and bit bar line /BL. Switch circuit units 51 and 52switch the I/O lines IO, /IO and bit lines BL, /BL according to a columndecoder signal Y_sw. An equalizing circuit 54 equalizes the bit linesBL, /BL according to an equalize signal EQ. A division circuit 55divides the bit lines BL, /BL according to a control signal ISO.

FIG. 3 (Prior Art) is a timing diagram of an array operation of theconventional synchronous memory device. The operation of theconventional synchronous memory device is controlled according to acommand signal CMD synchronous with an external clock signal CLK. In thecommand signal CMD, ACT means active command, WT means write command, RDmeans read command, and PRE means precharge command. In FIG. 3, SAEN isa sense amplifier enable signal, BL and /BL are bit line signals, CELLis a voltage signal of a memory cell, Y_sw is a column decoder signal.And in FIG. 3, VDD indicates power supply voltage, VPP indicates highvoltage, and VSS indicates substrate voltage.

Firstly, the memory array is controlled in an active state according tothe active command ACT (ACTIVE_STATE=high), a specific word line isselected according to the row address (Word Line=VDD˜VPP), and thus adata of the memory cell is applied to the bit line BL and the bit barline /BL according to charge sharing. Here, the bit line BL and the bitbar line /BL have a small potential difference due to a capacitanceratio between the memory cell and the bit line, which is sensed to awanted potential by the operation of the sense amplifier (SAEN=high).

Thereafter, when a column command signal R or W is externally inputted,data can be inputted to the memory device and outputted from the memorydevice through a date in/out pin(not shown in the figures) according tothe operation of the data IN/OUT buffer 24, the sense amplifier unit 46and the I/O unit 48. At this time, if a succeeding column command is thewrite command W and the inputted data is different from the data storedin the memory array, the bit line BL, the bit bar line /BL and thememory cell renew data of the memory cell according to the operationindicated by a dotted line of FIG. 3. The data of the memory cell arerenewed later than the data of the bit line BL and the bit bar line /BL.Such a delay is generated by a parasitic resistance element such as atransistor and a contact hole of the memory cell due to integration ofthe memory device.

After the column operation of the write and read operation, a datastorage state of the memory cell is normally maintained and theprecharge control signal PRE is applied to perform a succeeding rowaccess operation. When the precharge control signal PRE is inputted, thedata of the memory cell are maintained, the word line, the senseamplifier enable signal SAEN, the bit line BL and the bit bar line /BLare sequentially disabled, and the memory device is prepared to performthe succeeding row access operation. As described above, the operationof the conventional synchronous memory device is performed according tothe command CMD synchronous with clock signal CLK.

FIG. 4 (Prior Art) is a timing diagram of the write operation of theconventional synchronous memory device. When the active command signalACT synchronous with a rising period of clock signal CLK is inputted,the memory array is controlled in an active state (ACTIVE_STATE=high).Thereafter, when a write command signal WT is inputted in the activestate of the memory array (ACTIVE_STATE=high), a series of operationsare performed to input a write data through a DQ pin and store the datain the memory array. When the precharge control signal PRE is inputted,the active state signal ACTIVE_state of the memory array enabled in ahigh level is disabled in a low level. Accordingly, in the writeoperation of the conventional synchronous memory device, the activestate signal ACTIVE_state of the memory array is set to a high levelaccording to the active command signal ACT, and reset to a low levelaccording to the precharge control signal PRE.

FIG. 5 (Prior Art) is a circuit diagram illustrating the prechargecontrol signal generator of the conventional synchronous memory device.The precharge control signal generator 60 includes a controller 362receiving the write signal W from the command decoder 26, the testsignal TEST from the test mode detector 34 and the write enable signal/WEI from the command buffer 20, and controls a test mode state. An RSflip flop unit 364 latches the output signal from the controller 362. Apulse generator 366 detects a falling edge of the output signal FFOUTfrom the RS flip flop unit 364, and generates a short pulse and the testmode precharge control signal TPRE. OR gate 38 ORs the test modeprecharge control signal TPRE from the pulse generator 366 and theprecharge control signal PRE of a normal mode from the command decoder26, and generates the precharge control signal PRE.

The controller 362 includes an inverter 368 receiving the write signal Wfrom the command decoder 26, and outputting an inverted signal. Aninverter 367 receives the test signal TEST from the test mode detector34, and outputs an inverted signal. An OR gate 369 ORs the outputsignals from the inverters 367, 368. A NOR gate 370 NORs the outputsignal from the inverter 367 and the write enable signal /WEI from thecommand buffer 20.

The RS flip flop unit 364 includes a NAND gate 371 receiving the outputsignal from the OR gate 369 as a reset signal. A NAND gate 372 receivesthe output signal from the NOR gate 370 as a set signal. In addition,the output terminal of the NAND gate 371 is connected to the inputterminal of the NAND gate 372, and the output terminal of the NAND gate372 is connected to the output terminal of the NAND gate 371.

The pulse generator 366 includes a delay 373 delaying the output signalFFOUT from the RS flip flop unit 364 for a predetermined time. Aninverter 374 receives the output signal from the delay 373. A NOR gate375 NORs the output signal FFOUT from the RS flip flop unit 364 and theoutput signal from the inverter 374, and generates the test modeprecharge control signal TPRE.

The operation of the conventional precharge control signal generator 60will now be explained with reference to the operation timing diagram ofFIG. 6 (Prior Art). When the output signal from the test mode detector34 is maintained at a high level according to the test mode setting, ifthe write command WT is inputted, the write signal W generates a highlevel short pulse at the rising edge of the clock signal CLK. The writesignal W resets the RS flip flop unit 364 to maintain its output signalFFOUT in a high level. Thereafter, when the write enable bar signal /WEIis transited to a high level, the output signal FFOUT from the RS flipflop unit 364 is transited to a low level. In addition, the test modeprecharge control signal TPRE becomes a high level short pulse by thepulse generator 366, and the precharge control signal PRE from thecommand decoder 26 also becomes a high level short pulse.

Therefore, the conventional precharge control signal generator 60generates a precharge signal synchronous with the rising edge of theclock signal CLK according to the precharge control signal PRE, and aprecharge signal asynchronous from the clock signal CLK according to thetest mode precharge control signal TPRE.

However, the conventional synchronous memory device has a disadvantagein that the precharge control signal generator can generate theprecharge control signal for the test mode after input of the writecommand, when at least a hold time tWR of the write command elapses(refer to FIG. 6).

Accordingly, when the conventional synchronous memory device generatingthe precharge control signal according to the command signal intends toperform the test operation by using a tester having a lower frequencythan its operation speed, to shorten an interval between the commandsmore than a period of the clock signal for the test operation, or toperform an inverse operation thereon, the memory device cannot adjustthe interval between the commands due to the hold time of the command,and thus is not able to perform the test operation.

Moreover, the conventional synchronous memory device employs activecircuits and write/read circuits by commands, thus increasing a layoutarea.

SUMMARY OF THE INVENTION

The inventions claimed and described herein provide a synchronous memorydevice having an asynchronous precharge function which can perform atest operation regardless of performance of a memory tester system.

They also provide a synchronous memory device having an asynchronousprecharge function which can input an interval between commandsregardless of a clock period, by generating a precharge control signalasynchronous from an externally-inputted clock signal by using a clockenable signal or chip selector bar signal which is not synchronous withthe clock signal, when intending to generate the precharge controlsignal for a test mode after input of a read or write command.

Furthermore, the inventions claimed and described herein provide asynchronous memory device having an asynchronous precharge functionwhich allows for a reduced layout area by removing circuits that wouldotherwise be required for each command, by generating a prechargecontrol signal asynchronous from a clock signal.

The inventions provide a semiconductor memory device with a normal modeand a test mode. The memory device includes a memory cell array forstoring data; and a precharge control signal generator for generating aprecharge control signal in the test mode, by using a predeterminedcontrol signal which does not influence access to the data stored in thememory cell array, even when maintained in a high or low level in thetest mode.

The precharge control signal generator receives the predeterminedcontrol signal, outputs a signal having an identical state to thecontrol signal in the normal mode, and outputs a signal fixed in a highor low level in the test mode. Preferably, the precharge control signalgenerator includes a delay unit for equalizing a setting time of theprecharge control signal after input of a command in the normal mode toa setting time of the precharge control signal after input of thecontrol signal in the test mode. When input of the commands issynchronous with a rising edge of the clock signal in the normal mode,the precharge control signal generator generates the precharge controlsignal synchronously with the rising edge of the control signal in thetest mode.

In addition, a synchronous memory device having an asynchronousprecharge function includes a memory cell array unit having a pluralityof memory cells for storing a plurality of data. A CLK/CKE bufferreceives an external clock signal and a clock enable signal, andgenerates an internal clock signal and an internal clock enable signal.A command buffer receives external commands such as a chip selector barsignal, a ras bar signal, a cas bar signal and a write bar signal. Anaddress buffer receives external addresses. A data I/O bufferinputs/outputs data signals. A command and state unit receives theaddress signal from the address buffer, the internal clock signal fromthe CLK/CKE buffer, the output signal from the command buffer and theinternal clock enable signal from the precharge control signalgenerator, and generates control signals for controlling internaloperations. A mode register receives the address signal from the addressbuffer and the mode election signal from the command and state unit, andoutputs control signals for controlling operation modes. A row/columnaddress control and decoding circuit accesses a predetermined positionof the memory cell array unit according to the address signal from theaddress buffer, and controls a read/write operation. An I/O dataprocessing circuit controls data input/output in the read/writeoperation according to the output signal from the command and stateunit. An asynchronous precharge control signal generator receives theinternal precharge control signal from the command and state unit, theinternal clock enable signal from the CLK/CKE buffer and the test modesignal from the mode register, and generates the internal clock enablesignal and the precharge control signal.

The row/column address control and decoding circuit includes a row latchunit receiving the address signal from the address buffer, and latchinga row address signal. A row predecoder predecodes the row address signalfrom the row latch unit. A row decoder decodes the output signal fromthe row predecoder, and selects a word line of the memory cell arrayunit. A column latch unit receives the column address signal from theaddress buffer, and latches a column address signal. A column predecoderpredecodes the column address signal from the column latch unit. Acolumn decoder decodes the output signal from the column predecoder andselects a bit line of the memory cell array unit.

The I/O data processing circuit includes a sense amplifier unit sensingand amplifying data of the bit line, when data are written/read to/fromthe memory cell array unit. A read control unit controls the read datafrom the sense amplifier unit to be transmitted to the data I/O buffer.A write control unit controls the write data from the data I/O buffer tobe transmitted to the sense amplifier unit.

The precharge control signal generator includes a delay chain delayingthe internal clock enable signal from the CLK/CKE buffer for apredetermined time. An AND gate ANDs the test mode detection signal fromthe mode register for controlling a precharge mode and the output signalfrom the delay chain. An OR gate ORs the internal precharge controlsignal from the command and state unit and the output signal from theAND gate, and outputs the precharge control signal. An OR gate ORs thetest mode detection signal and the internal clock enable signal, andgenerates the internal clock enable signal.

The delay chain includes an even number of inverters.

According to another aspect of the present invention, a synchronousmemory device includes a memory cell array unit having a plurality ofmemory cells for storing a plurality of data. A CLK/CKE buffer receivesan external clock signal and a clock enable signal, and generates aninternal clock signal. A command buffer receives external commands suchas a chip selector bar signal, a ras bar signal, a cas bar signal and awrite bar signal. An address buffer receives external addresses. A dataI/O buffer inputs/outputs data signals. A command and state unitreceives the address signal from the address buffer, the internal clocksignal from the CLK/CKE buffer, the output signal from the commandbuffer and the internal chip selector bar signal from the prechargecontrol signal generator, and generates control signals for controllinginternal operations. A mode register receives the address signal fromthe address buffer and the mode selection signal from the command andstate unit, and outputs control signals for controlling operation modes.A row/column address control and decoding circuit accesses apredetermined position of the memory cell array unit according to theaddress signal from the address buffer, and controls a read/writeoperation. An I/O data processing circuit controls data input/output inthe read/write operation according to the output signal from the commandand state unit. An asynchronous precharge control signal generatorreceives the internal precharge control signal from the command andstate unit, the internal chip selector bar signal from the commandbuffer and the test mode signal from the mode register, and generatesthe internal chip selector bar signal and the precharge control signal.

The row/column address control and decoding circuit includes: a rowlatch unit receiving the address signal from the address buffer, andlatching a row address signal. A row predecoder predecodes the rowaddress signal from the row latch unit. A row decoder decodes the outputsignal from the row predecoder, and selects a word line of the memorycell array unit. A column latch unit receives the column address signalfrom the address buffer, and latches a column address signal. A columnpredecoder predecodes the column address signal from the column latchunit. A column decoder decodes the output signal from the columnpredecoder, and selects a bit line of the memory cell array unit.

The I/O data processing circuit includes a sense amplifier unit whichsenses and amplifies data of the bit line, when data are written/readto/from the memory cell array unit. A read control unit controls theread data from the sense amplifier unit to be transmitted to the dataI/O buffer. A write control unit controls the write data from the dataI/O buffer to be transmitted to the sense amplifier unit.

The precharge control signal generator includes a delay chain fordelaying the internal chip selector bar signal from the command bufferfor a predetermined time. An AND gate ANDs the test mode detectionsignal from the mode register for controlling a precharge mode and theoutput signal from the delay chain. An OR gate ORs the internalprecharge control signal from the command and state unit and the outputsignal from the AND gate and outputs the precharge control signal. AnAND gate ANDs an inverted signal of the test mode detection signal andthe internal chip selector signal, and generates the internal chipselector bar signal.

The delay chain includes an even number of inverters.

According to still another aspect of the present invention, asynchronous memory device receiving a command for a read/write operationsynchronously with an external clock signal, and having a memory cellstoring a plurality of data and an I/O circuit inputting/outputting thedata of the memory cell in the read/write operation, includes anasynchronous command input control signal generator for generating anasynchronous command input control signal asynchronous from the clocksignal according to an input pulse signal asynchronous from the clocksignal, and controlling input of an external command signal asynchronousfrom the clock signal according to the asynchronous command inputcontrol signal.

The input pulse signal asynchronous from the clock signal may be a clockenable signal. And the input pulse signal asynchronous from the clocksignal may be a chip selector bar signal.

As discussed earlier, the synchronous memory device having theasynchronous precharge function can input an interval between thecommands regardless of the clock period, by generating the prechargecontrol signal PRE by using the clock enable signal CLK or chip selectorbar signal /CS which is not synchronous with the clock signal CLK, whenintending to generate the precharge control signal PRE for the test modeafter input of the write command in the write operation.

Especially, in order to efficiently test a specific operation parameterof the high frequency synchronous memory device in a wafer or packagelevel and screen a defect thereof, the test operation should beperformed with a sufficient margin. The conventional synchronous DRAMusing the precharge control signal generator cannot obtain a sufficientmargin due to poor performance of the memory tester. However, thesynchronous memory device having the asynchronous precharge function inaccordance with the present invention can freely perform the testoperation, regardless of performance of the memory tester.

That is, the synchronous memory device of the present invention canperform the sufficient margin test operation in the wafer level, andthus replaces a defect memory cell by a redundancy memory cell in thewafer level, which results in an improved yield. Moreover, thesufficient margin test can also be carried out in the package test, toimprove quality.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become better understood with reference tothe accompanying drawings which are given only by way of illustrationand thus are not limitative of the present invention, wherein:

FIG. 1 (Prior Art) is a block diagram illustrating a conventionalsynchronous memory device;

FIG. 2 (Prior Art) is a block diagram illustrating a conventionalsynchronous memory array;

FIG. 3 (Prior Art) is an operation timing diagram of the conventionalsynchronous memory device;

FIG. 4 (Prior Art) is a timing diagram of a write operation of theconventional synchronous memory device;

FIG. 5 (Prior Art) is a circuit diagram illustrating a precharge controlsignal generator of the conventional synchronous memory device;

FIG. 6 (Prior Art) is an operation timing diagram of the prechargecontrol signal generator FIG. 5;

FIG. 7 is a block diagram illustrating a synchronous memory device inaccordance with a first embodiment of the present invention;

FIG. 8 is a circuit diagram illustrating a precharge control signalgenerator of FIG. 7;

FIG. 9 is a timing diagram of the write operation in a test mode of thesynchronous memory device having the precharge control signal generatorof FIG. 8;

FIG. 10 is a block diagram illustrating a synchronous memory device inaccordance with a second embodiment of the present invention;

FIG. 11 is a circuit diagram illustrating a precharge control signalgenerator of FIG. 10; and

FIG. 12 is a timing diagram of the write operation in a test mode of thesynchronous memory device having the precharge control signal generatorof FIG. 11.

DETAILED DESCRIPTION

A precharge control signal generator and a semiconductor memory deviceusing the same in accordance with preferred embodiments of the presentinvention will now be described in detail with reference to FIGS. 7through 11.

FIG. 7 is a block diagram illustrating a synchronous memory device inaccordance with a first embodiment of the present invention. Thesynchronous memory device includes a CLK/CKE buffer 130 externallyreceiving and buffering a clock signal CLK and a clock enable signalCKE, and generating an internal clock signal iCLK and an internal clockenable signal iCKE. A command buffer 126 receives external commands suchas a chip selector bar signal /CS, a ras bar signal /RAS, a cas barsignal /CAS and a write bar signal /WE. An address buffer 122 receivesexternal addresses A0˜Ai; and a data I/O buffer 120 inputting/outputtingdata signals DQ0˜DQj.

In addition, the synchronous memory device includes a command and stateunit 128 for receiving the address signal from the address buffer 122,the internal clock signal iCLK from the CLK/CKE buffer 130, the outputsignal from the command buffer 126 and the internal clock enable signaliCKEn from the precharge control signal generator 140, and generatingcontrol signals for controlling internal operations. And the command andstate unit 128 generates read command RD and write command WT. A moderegister 124 receives the output signal from the address buffer 122 andthe mode selection signal MS from the command and state unit 128, andoutputs control signals CL, BL, TEST for controlling operation modes. Anasynchronous precharge control signal generator 140 receives theinternal precharge control signal iPRE from the command and state unit128, the internal clock enable signal iCKE from the CLK/CKE buffer 130and the test mode signal TEST from the mode register 124, and generatesthe precharge control signal PRE and the internal clock enable signaliCKEn.

The synchronous memory device also includes a memory cell array unit 100having a plurality of memory cells for storing data. A row/columnaddress control and decoding circuit 160 accesses a predeterminedposition of the memory cell array unit 100, and controls a read/writeoperation. An I/O data processing circuit 170 controls data input/outputin the read/write operation.

The row/column address control and decoding circuit 160 includes a rowlatch unit 106 receiving the address signal from the address buffer 122,and latching a row address latch signal. A row predecoder 104 predecodesthe row address latch signal from the row latch unit 106. A row decoder102 decodes the output signal from the row predecoder 104, and selects aword line of the memory cell array unit 100. A column latch unit 110receives the column address signal from the address buffer 122, andlatches a column address signal. A column predecoder 108 predecodes thecolumn address signal from the column latch unit 110. A column decoder112 decodes the output signal from the column predecoder 108, andselects a bit line of the memory cell array unit 100.

The I/O data processing circuit 170 includes a sense amplifier unit 114accessing the memory cell array unit 100, and sensing and amplifyingdata of a bit line, when data are written/read to/from the memory cellarray unit 100. A read control unit 116 controls the read data from thesense amplifier unit 114 to be transmitted to the data I/O buffer 120. Awrite control unit 118 controls the write data from the data I/O buffer120 to be transmitted to the sense amplifier unit 114.

As illustrated in FIG. 8, the precharge control signal generator 140includes a delay chain 142 delaying the internal clock enable signaliCKE from the CLK/CKE buffer 130 for a predetermined time. The delaychain 142 comprises buffers 143, 144. An AND gate 145 ANDs the test modedetection signal TEST from the mode register 124 for controlling aprecharge mode and the output signal from the delay chain 142. An ORgate 146 ORs the internal precharge control signal iPRE from the commandand state unit 128 and the output signal from the AND gate 145, andoutputs the precharge control signal PRE. An OR gate 141 ORs the testmode detection signal TEST and the internal clock enable signal iCKE,and generates the internal clock enable signal iCKEn.

FIG. 9 is a timing diagram of the write operation in the test mode(TEST=high) of the synchronous memory device having the prechargecontrol signal generator 140 of FIG. 8. In FIG. 9, CKE is a clock enablesignal, CLK is a clock signal, CMD is a command signal, Din is a inputdata signal, PRE is a precharge control signal, ACTIVE_state is activestate signal. An active state signal ACTIVE_state of a cell array blockis set/reset according to input of the active command ACTi, the writecommand WTi and the precharge command PREi which are synchronous withthe clock signal CLK and input of the clock enable signal CKEasynchronous from the clock signal. The rising edge of the clock signalCLK and that of the clock enable signal CKE have a delay time tRWL.

The active state signal ACTIVE_state showing an active state of the cellarray block is reset according to a rising edge of the clock enablesignal CKE. According to the position of the rising edge of the clockenable signal CKE, a test operation can be performed even when aninterval between the commands has a minus value. In addition, theprecharge control signal PRE is generated by using the clock enablesignal CKE which does not influence access to the memory cell data, whenthe test mode detection signal TEST is internally fixed to a high or lowlevel in the test operation. It is thus possible to input a commandasynchronous from the clock signal.

The delay chain 142 can test a time difference between the prechargecontrol signal PRE in the normal operation according to input of theprecharge command PREi, and the precharge control signal PRE in the testmode according to asynchronous input of the clock enable signal CKE,thereby easily compensating for the time difference by the test result.

The rising edge of the clock enable signal CKE is used because thecommand input is synchronous with the rising edge of the clock signalCLK in the normal operation. It is useful in a low performance testsystem when a signal has a high rising/falling transition timedifference.

In the precharge control signal generator 140, when a current mode isnot the test mode (TEST=low), the internal clock enable signal iCKEn isequalized to the internal clock enable signal iCKE from the CLK/CKEbuffer 130. In the test mode (TEST=high), the internal clock enablesignal iCKEn becomes a high level, regardless of a state of the internalclock enable signal iCKE.

Therefore, the precharge control signal generator 140 generates theprecharge control signal PRE according to the precharge command PREisynchronous with the clock signal CLK, or the clock enable signal. CKEwhich does not relate to the clock signal CLK.

FIG. 10 is a block diagram illustrating a synchronous memory device inaccordance with a second embodiment of the present invention. In thefollowing description, same drawing reference numerals are used todenote like or corresponding elements. The synchronous memory deviceincludes a CLK/CKE buffer 130 externally receiving and buffering a clocksignal CLK and a clock enable signal CKE, and generating an internalclock signal iCLK and an internal clock enable signal iCKE. A commandbuffer 126 receives external commands such as a chip selector bar signal/CS, a ras bar signal /RAS, a cas bar signal /CAS and a write bar signal/WE. An address buffer 122 receives external addresses A0˜Ai; and a dataI/O buffer 120 inputs/outputs data signals DQ0˜DQj.

In addition, the synchronous memory device includes a command and stateunit 228 receiving the address signal from the address buffer 122, theinternal clock signal iCLK from the CLK/CKE buffer 130, the outputsignal from the command buffer 126 and the internal chip selector barsignal /iCSn from the precharge control signal generator 240, andgenerates control signals for controlling internal operations. A moderegister 124 receives the output signal from the address buffer 122 andthe mode selection signal MS from the command and state unit 228, andoutputs control signals CL, BL, TEST for controlling operation modes. Anasynchronous precharge control signal generator 240 receives theinternal precharge control signal iPRE from the command and state unit228, the internal chip selector bar signal /CS from the command buffer126 and the test mode signal TEST from the mode register 124, andgenerates the precharge control signal PRE and the internal chipselector bar signal /iCSn.

The synchronous memory device also includes a memory cell array unit 100having a plurality of memory cells for storing data. A row/columnaddress control and decoding circuit 160 accesses a predeterminedposition of the memory cell array unit 100, and controls a read/writeoperation. An I/O data processing circuit 170 controls data input/outputin the read/write operation.

The row/column address control and decoding circuit 160 includes a rowlatch unit 106 receiving the address signal from the address buffer 122,and latching a row address latch signal. A row predecoder 104 predecodesthe row address latch signal from the row latch unit 106. A row decoder102 decodes the output signal from the row predecoder 104, and selects aword line of the memory cell array unit 100. A column latch unit 110receives the column address signal from the address buffer 122, andlatches a column address signal. A column predecoder 108 predecodes thecolumn address signal from the column latch unit 110. A a column decoder112 decodes the output signal from the column predecoder 108, andselects a bit line of the memory cell array unit 100.

The I/O data processing circuit 170 includes a sense amplifier unit 114accessing the memory cell array unit 100, and senses and amplifies dataof a bit line, when data are written/read to/from the memory cell arrayunit 100. A read control unit 116 controls the read data from the senseamplifier unit 114 to be transmitted to the data I/O buffer 120. A writecontrol unit 118 controls the write data from the data I/O buffer 120 tobe transmitted to the sense amplifier unit 114.

As shown in FIG. 11, the precharge control signal generator 240 includesa delay chain 242 delaying the internal chip selector bar signal /iCSfrom the command buffer 126 for a predetermined time. An AND gate 248ANDs the test mode detection signal TEST from the mode register 124 forcontrolling a precharge mode and the output signal from the delay chain242. An OR gate 250 ORs the internal precharge control signal iPRE fromthe command and state unit 228 and the output signal from the AND gate248, and outputs the precharge control signal PRE. An AND gate 252 ANDsan inverted signal of the test mode detection signal TEST and theinternal chip selector signal iCSB, and generates the internal chipselector bar signal iCSn.

FIG. 12 is a timing diagram of the write operation in the test mode(TEST=high) of the synchronous memory device having the prechargecontrol signal generator 240 of FIGS. 10 and 11. An active state signalACTIVE_state activating the memory cell array unit 100 is set/resetaccording to a rising period of the precharge command signal PREsynchronous with the clock signal CLK and a falling period of the chipselector bar signal /CS asynchronous from the clock signal CLK.

The active state signal ACTIVE_state showing an active state of the cellarray block is reset according to a rising edge of the chip selector barsignal /CS. According to the position of the rising edge of the clockenable signal CKE, a test operation can be performed even when aninterval between the commands has a minus value. In addition, theprecharge control signal PRE is generated by using the chip selector barsignal /CS which does not influence access to the memory cell data, whenthe test mode detection signal TEST is internally fixed to a high or lowlevel in the test operation. It is thus possible to input a commandasynchronous from the clock signal.

The delay chain 246 can test a time difference between the prechargecontrol signal PRE in the normal operation according to input of theprecharge command PREi, and the precharge control signal PRE in the testmode according to asynchronous input of the chip selector bar signal/CS, thereby easily compensating for the time difference by the testresult.

The rising edge of the chip selector bar signal /CS is used because thecommand input is synchronous with the rising edge of the clock signalCKL in the normal operation. It is useful in a low performance testsystem when a signal has a high rising/falling transition timedifference.

In the precharge control signal generator 240, when a current mode isnot the test mode (TEST=low), the internal chip selector bar signal/iCSn is equalized to the internal chip selector bar signal /iCS fromthe command buffer 126. In the test mode (TEST=high), the internal chipselector bar signal /iCSn becomes a high level, regardless of a state ofthe internal chip selector bar signal /iCS.

Therefore, the precharge control signal generator 240 generates theprecharge control signal PRE according to the precharge command PREisynchronous with the clock signal CLK, or the chip selector bar signal/CS which does not relate to the clock signal CLK.

As discussed earlier, the synchronous memory device having theasynchronous precharge function can input an interval between thecommands regardless of the dock period, by generating the prechargecontrol signal PRE by using the clock enable signal CKE or chip selectorbar signal /CS which is not synchronous with the clock signal CLK, whenintending to generate the precharge control signal PRE for the test modeafter input of the write command in the write operation.

In order to efficiently test a specific operation parameter of the highfrequency synchronous memory device in a wafer or package level andscreen a defect thereof, the test operation should be performed with asufficient margin. The conventional synchronous DRAM using the prechargecontrol signal generator cannot obtain a sufficient margin due to poorperformance of the memory tester. However, the synchronous memory devicehaving the asynchronous precharge function in accordance with thepresent invention can freely perform the test operation, regardless ofperformance of the memory tester.

That is, the synchronous memory device of the present invention canperform the sufficient margin test operation in the wafer level, andthus replaces a defect memory cell by a redundancy memory cell in thewafer level, which results in an improved yield. Moreover, thesufficient margin test can also be carried out in the package test, toimprove quality.

As the present invention may be embodied in several forms withoutdeparting from the spirit or essential characteristics thereof, itshould also be understood that the above-described embodiments are notlimited by any of the details of the foregoing description, unlessotherwise specified, but rather should be construed broadly within itsspirit and scope as defined in the appended claims, and therefore allchanges and modifications that fall within the meets and bounds of theclaims, or equivalences of such meets and bounds are intended to beembraced by the appended claims.

What is claimed is:
 1. A semiconductor memory device with a normal modeand a test mode, comprising: a memory cell array for storing data; and aprecharge control signal generator for generating a precharge controlsignal in the test mode, by using a predetermined control signal whichdoes not influence access to the data stored in the memory cell array,even when maintained in a high or low level in the test mode.
 2. Thedevice according to claim 1, wherein the precharge control signalgenerator receives the predetermined control signal, outputs a signalhaving an identical state to the control signal in the normal mode, andoutputs a signal fixed in a high or low level in the test mode.
 3. Thedevice according to claim 1, wherein the precharge control signalgenerator includes a delay unit for equalizing a setting time of theprecharge control signal after input of a command in the normal mode toa setting time of the precharge control signal after input of thecontrol signal in the test mode.
 4. The device according to claim 1,wherein, when input of commands is synchronous with a rising edge of theclock signal in the normal mode, the precharge control signal generatorgenerates the precharge control signal synchronously with the risingedge of the control signal in the test mode.
 5. A precharge controlsignal generator for a semiconductor memory device with a normal modeand a test mode, comprising: an internal control signal generator forreceiving a predetermined control signal which does not influence accessto a memory cell data in the test mode, outputting a signal fixed in ahigh or low level in the test mode, and outputting a signal having anidentical state to the control signal in the normal mode; a delay unitfor delaying the control signal in the test mode as long as a settingtime of a precharge control signal after input of a command in thenormal mode; and a logic gate for ORing the precharge control signal ofthe normal mode and the output signal from the delay unit.
 6. Asynchronous memory device comprising: a memory cell array unit having aplurality of memory cells for storing a plurality of data; a CLK/CKEbuffer externally receiving a clock signal and a clock enable signal,and generating an internal clock signal and an internal clock enablesignal; a command buffer receiving external commands such as a chipselector bar signal, a ras bar signal, a cas bar signal and a write barsignal; an address buffer receiving external addresses; a data I/Obuffer inputting/outputting data signals; a command and state unitreceiving the address signal from the address buffer, the internal clocksignal from the CLK/CKE buffer, the output signal from the commandbuffer and the internal clock enable signal from the precharge controlsignal generator, and generating control signals for controllinginternal operations; a mode register receiving the address signal fromthe address buffer and the mode selection signal from the command andstate unit, and outputting control signals for controlling operationmodes; a row/column address control and decoding circuit accessing apredetermined position of the memory cell array unit according to theaddress signal from the address buffer, and controlling a read/writeoperation; an I/O data processing circuit controlling.data input/outputin the read/write operation according to the output signal from thecommand and state unit; and an asynchronous precharge control signalgenerator receiving the internal precharge control signal from thecommand and state unit, the internal clock enable signal from theCLK/CKE buffer and the test mode signal from the mode register, andgenerating the internal clock enable signal and a precharge controlsignal.
 7. The device according to claim 6, wherein the row/columnaddress control and decoding circuit comprises: a row latch unitreceiving the address signal from the address buffer, and latching a rowaddress signal; a row predecoder predecoding the row address signal fromthe row latch unit; a row decoder decoding the output signal from therow predecoder, and selecting a word line of the memory cell array unit;a column latch unit receiving the column address signal from the addressbuffer, and latching a column address signal; a column predecoderpredecoding the column address signal from the column latch unit; and acolumn decoder decoding the output signal from the column predecoder,and selecting a bit line of the memory cell array unit.
 8. The deviceaccording to claim 6, wherein the I/O data processing circuit comprises:a sense amplifier unit sensing and amplifying data of the bit line, whendata are written/read to/from the memory cell array unit; a read controlunit controlling the read data from the sense amplifier unit to betransmitted to the data I/O buffer; and a write control unit controllingthe write data from the data I/O buffer to be transmitted to the senseamplifier unit.
 9. The device according to claim 6, wherein theprecharge control signal generator comprises: a delay chain delaying theinternal clock enable signal from the CLK/CKE buffer for a predeterminedtime; an AND gate ANDing the test mode detection signal from the moderegister for controlling a precharge mode and the output signal from thedelay chain; an OR gate ORing the internal precharge control signal fromthe command and state unit and the output signal from the AND gate, andoutputting the precharge control signal; and an OR gate ORing the testmode detection signal and the internal clock enable signal, andgenerating the internal clock enable signal.
 10. The device according toclaim 9, wherein the delay chain consists of an even number ofinverters.
 11. A synchronous memory device comprising: a memory cellarray unit having a plurality of memory cells for storing a plurality ofdata; a CLK/CKE buffer externally receiving a clock signal and a clockenable signal, and generating an internal clock signal; a command bufferreceiving external commands such as a chip selector bar signal, a rasbar signal, a cas bar signal and a write bar signal; an address bufferreceiving external addresses; a data I/O buffer inputting/outputtingdata signals; a command and state unit receiving the address signal fromthe address buffer, the internal clock signal from the CLK/CKE buffer,the output signal from the command buffer and the internal chip selectorbar signal from the precharge control signal generator, and generatingcontrol signals for controlling internal operations; a mode registerreceiving the address signal from the address buffer and the modeselection signal from the command and state unit, and outputting controlsignals for controlling operation modes; a row/column address controland decoding circuit accessing a predetermined position of the memorycell array unit according to the address signal from the address buffer,and controlling a read/write operation; an I/O data processing circuitcontrolling data input/output in the read/write operation according tothe output signal from the command and state unit; and an asynchronousprecharge control signal generator receiving the internal prechargecontrol signal from the command and state unit, the internal chipselector bar signal from the command buffer and the test mode signalfrom the mode register, and generating the internal chip selector barsignal and a precharge control signal.
 12. The device according to claim11, wherein the row/column address control and decoding circuitcomprises: a row latch unit receiving the address signal from theaddress buffer, and latching a row address signal; a row predecoderpredecoding the row address signal from the row latch unit; a rowdecoder decoding the output signal from the row predecoder, andselecting a word line of the memory cell array unit; a column latch unitreceinving the column address signal from the address buffer, andlatching a column address signal; a column predecoder predecoding thecolumn address signal from the column latch unit; and a column decoderdecoding the output signal from the column predecoder, and selecting abit line of the memory cell array unit.
 13. The device according toclaim 11, wherein the I/O data processing circuit comprises: a senseamplifier unit sensing and amplifying data of the bit line, when dataare written/read to/from the memory cell array unit; a read control unitcontrolling the read data from the sense amplifier unit to betransmitted to the data I/O buffer; and a write control unit controllingthe write data from the data I/O buffer to be transmitted to the senseamplifier unit.
 14. The device according to claim 11, wherein theprecharge control signal generator comprises: a delay chain delaying theinternal chip selector bar signal from the command buffer for apredetermined time; an AND gate ANDing the test mode detection signalfrom the mode register for controlling a precharge mode and the outputsignal from the delay chain; an OR gate ORing the internal prechargecontrol signal from the command and state unit and the output signalfrom the AND gate, and outputting the precharge control signal; and anAND gate ANDing an inverted signal of the test mode detection signal andthe internal chip selector signal, and generating the internal chipselector bar signal.
 15. The device according to claim 14, wherein thedelay chain consists of an even number of inverters.